Technological innovations in semiconductor fabrication technologies are driving market demands for semiconductor memory devices providing higher storage capacity, higher speed, higher integration density, and lower power consumption. The downscaling of semiconductor memory devices to submicron design rules and beyond, however, coupled with increased storage capacity poses technological challenges with respect to maintaining performance and reliability. For instance, as memory capacity increases and the pitch between adjacent patterns are made narrower, the layout of the memory arrays and peripheral devices become more problematic, especially with regard to memory core layout. When designing memory circuits, it is desirable to minimize the length and loading of wordlines. Indeed, if wordlines are too long/narrow and/or have too many memory cells connected to each wordline (i.e., a large load), wordline enable driver circuits will consume more power to drive the wordlines, and the speed of driving wordlines can decrease. To mitigate the impact on device performance with line rule downscaling and increased memory density, various memory circuit architectures have been employed including, for example, hierarchical memory bank architectures and hierarchical word line driver structures with sub word line architectures.
For instance, FIGS. 1A˜1C are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework. FIG. 1A illustrates a semiconductor integrated circuit memory chip (10) having a memory cell array with a memory capacity of 1 Gb, which is divided into a plurality of memory banks, Bank A, B, C and D (or more generally, Bank-i) (e.g., 4 memory banks of 256 Mb). Each memory bank Bank-i can be independently operated with associated peripheral circuits including column decoders (11) and row decoders (12), and well as other I/O circuitry for outputting/inputting data via peripheral data I/O pads (13). Each memory bank Bank-i comprises decoder circuits and core circuits that are arranged in “unit blocks,” as depicted in FIG. 1B. In particular, FIG. 1B schematically illustrates a conventional layout of each memory bank (Bank_i) in FIG. 1A, wherein each memory bank (Bank-i) comprises a plurality of 256 unit blocks BL(i) including 16 unit blocks along an x-direction (bitline/column direction) and 16 unit blocks along a y-direction (wordline/row direction).
FIG. 1C schematically illustrates a conventional layout pattern for each unit block BL-i in the memory bank Bank-i for a memory device utilizing a hierarchical sub-word line driver scheme. Each unit block BL-i includes a cell array (20), sub-word line driver (SWD) arrays (21), bit line sense amplifier (BSLA) arrays (23) and conjunction circuit blocks including PXiD driver blocks (22) and LA driver (LADRV) blocks (24). The unit block pattern BL-i depicted in FIG. 1C is repeated in both x and y directions over the memory bank Bank-i such that each memory cell array block (20) is disposed between two BLSA blocks (23) in the x (column) direction of bit lines and such that each memory cell array block (20) is disposed between two sub-word line drivers (21) in the y (wordline) direction. In one conventional hierarchical word line framework, each block sense amplifier (23) is shared by two memory cell array blocks (20) to the left and right of the BLSA (23) and each sub-word line driver (21) is shared by two memory cell array blocks (20) above and below the SWD block (21) using an interleaved layout framework, as is known in the art.
By way of specific example, FIG. 2A is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in FIG. 1C in a semiconductor device having a hierarchical divided wordline scheme. As shown in FIG. 2A, a memory cell array (200) includes an array of memory cells MC (each having a cell transistor and cell capacitor in a DRAM memory) located at the intersection of a bit line BL or BLB and a sub-word line WL. The bit lines are connected to the memory cells MC and to corresponding sense amplifiers SA in BLSA blocks (230) and (231) using an open bitline architecture, for example, as is known in the art. The BSLA blocks (230) and (231) are driven by control signals generated by drivers in respective LADRV blocks (240) and (241). In the hierarchical divided wordline scheme, a wordline is divided into a plurality of sub-wordlines WL that are driven using corresponding sub-wordline driver blocks (210) and (211) located above and below the memory cell array (200). In the exemplary embodiment of FIG. 2A, there are 256 sub word lines WL that are connected to the memory cells in corresponding rows of memory cells (where the rows extend in the Y-direction). The SWD array (210) includes a plurality of sub word line driver SWD circuits that are connected to and drive the even sub wordlines (WLO, WL2, . . . WL252, WL254) in the array (200) and a memory cell array of next lower unit block below. The SWD array (211) includes a plurality of sub word line driver circuits that are connected to and drive the odd sub wordlines WL1, WL3, . . . WL253, WL255 in the array (200) as well as a memory cell array of a next upper unit block.
The SWDs in the SWD arrays (210) and (211) are connected to normal (main) wordlines NWE and sub wordline enable lines from respective PXiD drivers (220) and (221), respectively. Each SWD circuit in the even SWD array (210) drives a corresponding even sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers (220). Each SWD circuit in the odd SWD array (211) drives a corresponding odd sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers (221). The PXiD driver blocks (220) and (221) are connected to word lines PXI<0:3>, where each normal wordline NWE-i controls a group of 4 subwordlines, wherein a given subwordline in the group is activated in response to a corresponding one of the wordlines PXI (0, 1, 2, 3). For instance, NWE (0) controls subwordlines WL0, WL1, WL2, and WL3 in response to wordline enable signals PXi<0-3>, NWE (1) controls subwordlines WL4, WL5, WL6 and WL7 in response to wordline enable signals PXi<0-3> and NWE (63) controls subwordlines WL252, WL253, WL254, and WL255 in response to wordline enable signals PXi<0-3>. With reference to FIG. 1B, there is a set of normal wordline enable lines NWE(0)-NEW(63) that extends in the y-direction for each alternating even/odd column of 16 blocks (in the y direction) such that each odd and even SWD block in each even and odd column is connected to each NWE line of the corresponding set of normal wordline enable lines NWE(0)-NEW(63).
FIG. 2B schematically illustrates an exemplary embodiment of the PXiD driver (220) and the SWD array (210) of FIG. 2A. The PXiD driver (220) comprises a PXiD generator (220a), a PXiDB generator (220b) and a PXiDG generator (220c). The SWD array (210) comprises a plurality of SWD circuits (SWD0, 2, 4, . . . 14) which are connected to and drive corresponding even subwordlines WL0, WL2, WL4, . . . , WL14). Each NWE is connected to a pair of adjacent even SWDs in the even SWD array (220) as well as a corresponding pair of adjacent odd SWDs in the odd SWD array (211) (not specifically shown in FIG. 2B). The PXiD generator (220a), PXiDB generator (220b) and PXiDG generator (220c) generate word line activation control signals that are output on line PxID(0)/PXIDB(0)/PXiDG(0) to activate the subword line drivers (SWD(0), SWD(4), SWD(8), . . . ) in each group of 4 sub word lines, as well as word line activation control signals that are output on lines PxID(2)/PXIDB(2)/PXiDG(2) to activate the subword drivers (SWD(2), SWD(6), SWD(10), . . . ) in each group of 4 sub wordlines.
FIG. 3 is a flow chart that illustrates a method for accessing memory in a semiconductor memory device having a hierarchical wordline scheme such as described above. In general, for a given memory bank, Bank-I, a 12 bit address (A0, . . . A11) is decoded to activate a sub wordline within one of the 256 memory cell arrays of the unit blocks. The upper four bits (A8, A9, A10, A11) are decoded to select 1 of 16 of the adjacent vertical memory blocks (step 30) (n4=16). The next seven upper address bits A2˜A7 are decoded by a row decoder to generate one of 64 normal word line enable signals NWE<0:63>. The lower two address bits A0, A1 are decoded by PXI decoders to drive a corresponding one of the sub word lines PXI<0:3>. As a result, one sub wordline out of the groups of 4 sub wordlines associated with the selected NWE is active where 4K bits of memory cells are enabled.
FIG. 4 illustrates a conventional sub word line driver circuit (40), which may be implemented for the SWDs in the even and odd SWD arrays (220) and (221) of FIG. 2A, for example. In general, a sub-word line driving circuit (40) drives a sub-word line WL in response to control signals NWE, PXID, PXIDG and PXIDB, and includes NMOS transistors T1, T2, T3 and T4. The sub word line driver (40) includes four control input nodes connecting to PXiD, PXiDG, PXiDB and NWE control signal lines, two power nodes for VPP and VSS and an output node N5 connected to a subword line WL. The NMOS transistor T3 has a channel connected between the NWE input (node N4) and a node N5 and a gate G3 connected to the word line activation signal PXiDG. The NMOS transistor T2 has a channel connected between control input node N1 (signal PXiD) and the output node N5 and a gate G2 connected to a boosting node N3. The NMOS transistor T1 has a channel connected between the gate G2 of transistor T2 and the NWE input node N4 and a gate G1 connected to the power voltage VPP input. The NMOS transistor T4 has a channel connected between the output node N5 and ground voltage node VSS and a gate G4 connected to a control signal input node PXiDB.
FIG. 5 is a timing diagram that illustrates operation of the sub-word line driver (40) of FIG. 4. In particular, FIG. 5 illustrates various voltage waveforms of control voltages NWEi, PXiD, PXiDB and PXiDG that are applied to drive a subwordline WLi. At time to, before an active operation, all of the signal lines shown in FIG. 5 are at Vss except PXIDB, which is an active low level IVCC that is applied to the gate G4 of transistor T4 to cause the WL at node N5 to be pulled down to VSS such that sub-word lines WL are precharged to Vss. At time t1, when a corresponding word line enable signal NWEi is activated, the boosting node N3 is charged from VSS to VPP-Vth by an overlap capacitance existing between the gate G2 and drain (N1) of the transistor T2 (where Vth denotes a threshold voltage of the NMOS transistor T1). Therefore, the boosted voltage VPP is supplied to the sub-word line WL through the NMOS transistor T2. At time t2, the control voltage PXiDB transitions to VSS causing transistor T4 to turn off. At time t3, the control signals PXID and PXIDG are asserted. The control signal PXiD is enabled to VPP, which causes the voltage at boosting node N3 to increase to 2 Vpp-Vth. This causes the corresponding sub-word line driver SWD to drive the corresponding sub-word line to Vpp. The NMOS transistor T3 serves to maintain the sub-word line WL in logic “low” state when the main word line driving signal NWE is in logic “low” state and the sub-word line driving signal PXID is in logic “high” state. After the access operation is complete, the sub-word line driver precharges the sub-word line WL to Vss.
Conventional semiconductor memory devices having a sub word line driver structure as described above may have an increased layout area due to the presence of the sub wordline driver arrays between the memory arrays. When designing semiconductor memory devices with sub word line driver framework, it is important to minimize the layout area required for the sub wordline drivers. Indeed, the layout area of the sub word line driving circuits has a significant influence upon the overall operating efficiency of the device memory device and the level of integration that may be achieved.